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Freescale Semiconductor /MK61F15WS /DDR /CR45

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Interpret as CR45

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)P0PRI00RESERVED 0 (0000)P0PRI10RESERVED 0 (0000)P0PRI20RESERVED 0 (0000)P0PRI30RESERVED

P0PRI3=0000, P0PRI0=0000, P0PRI2=0000, P0PRI1=0000

Description

DDR Control Register 45

Fields

P0PRI0

Port 0 Priority 0 commands

0 (0000): Lowest

1 (0001): -----

14 (1110): -----

15 (1111): Highest
RESERVED

Reserved
P0PRI1

Port 0 Priority 1 commands

0 (0000): Lowest

1 (0001): -----

14 (1110): -----

15 (1111): Highest
RESERVED

Reserved
P0PRI2

Port 0 Priority 2 commands

0 (0000): Lowest

1 (0001): -----

14 (1110): -----

15 (1111): Highest
RESERVED

Reserved
P0PRI3

Port 0 Priority 3 commands

0 (0000): Lowest

1 (0001): -----

14 (1110): -----

15 (1111): Highest
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data